Channel Plus 8052 Spezifikationen

MicroConverter® Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU Data Sheet ADuC845/ADuC847/ADuC848 Rev. C Documen

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 10 of 108 ABOSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter Rating

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 100 of 108 Table 69. SPI MASTER MODE TIMING (CPHA = 0) Parameter Min Typ Max Unit tSL

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 101 of 108 Table 70. SPI SLAVE MODE TIMING (CPHA = 1) Parameter Min Typ Max Unit tSS

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 102 of 108 Table 71. SPI SLAVE MODE TIMING (CPHA = 0) Parameter Min Typ Max Unit tSS SS to SCL

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 103 of 108 Table 72. UART TIMING (SHIFT REGISTER MODE) Parameter 12.58 MHz Core_Clk Variable Cor

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 104 of 108 OUTLINE DIMENSIONS COMPLIANT TO JEDEC STANDARDS MO-112-AC-1SEATINGPLANEVIEW A2.45MAX1.03

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 105 of 108 ORDERING GUIDE Model1, 2, 3 Temperature Range Package Description Package Option ADu

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 106 of 108 NOTES

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 107 of 108 NOTES

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 108 of 108 NOTES Purchase of licensed I2C components of Analog Device

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 11 of 108 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 52 51 50 49 48 43 42 41 4047 46 45 4414 15 1

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 12 of 108 Pin No: 52-MQFP Pin No: 56-LFCSP Mnemonic Type1 Description 9 9 P1.4/AIN5 I On pow

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 13 of 108 Pin No: 52-MQFP Pin No: 56-LFCSP Mnemonic Type1 Description 20, 34, 48 22, 36, 51 DVDD

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 14 of 108 Pin No: 52-MQFP Pin No: 56-LFCSP Mnemonic Type1 Description 43–46, 49–52 46–49, 52–55

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 15 of 108 GENERAL DESCRIPTION The ADuC845, ADuC847, and ADuC848 are single-cycle, 12.58 MIPs, 8052

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 16 of 108 WATCHDOGTIMER2304 BYTESUSER RAMPOWER SUPPLYMONITORTEMPSENSOR200A200ABAND GAPREFERENCEVRE

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 17 of 108 WATCHDOGTIMER2304 BYTESUSER RAMPOWER SUPPLYMONITOR200A200ABAND GAPREFERENCEVREFDETECTAVD

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 18 of 108 WATCHDOGTIMER2304 BYTESUSER RAMPOWER SUPPLYMONITOR200µA200µABAND GAPREFERENCEVREFDETECTAV

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 19 of 108 COMPLETE SFR MAP RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 2 of 108 TABLE OF CONTENTS Specifications ...

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 20 of 108 FUNCTIONAL DESCRIPTION 8051 INSTRUCTION SET Table 4. Optimized Single-Cycle 8051 Instruct

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 21 of 108 Mnemonic Description Bytes Cycles1 RLC A Rotate A left through carry 1 1 RR A Rota

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 22 of 108 Mnemonic Description Bytes Cycles1 SJMP rel Short jump (relative address) 2 3 JC re

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 23 of 108 1110010007H0FH17H1FH2FH7FH00H08H10H18H20HRESET VALUE OFSTACK POINTER30HFOUR BANKS OF EIGH

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 24 of 108 SPECIAL FUNCTION REGISTERS (SFRs) The SFR space is mapped into the upper 128 bytes of int

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 25 of 108 Power Control Register (PCON) The PCON SFR contains bits for power-saving options and gen

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 26 of 108 ADC CIRCUIT INFORMATION The ADuC845 incorporates two 10-channel (8-channel on the MQFP pa

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 27 of 108 Signal Chain Overview (Chop Enabled, CHOP = 0) With the CHOP bit = 0 (see the ADCMODE SFR

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 28 of 108 This offset is removed by performing a running average of 2. This average by 2 means that

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 29 of 108 ADC Noise Performance with Chop Enabled (CHOP = 0) Table 10, Table 11, Table 12, and Tabl

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 3 of 108 Power-On Reset Operation ... 88 Power

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 30 of 108 Signal Chain Overview with Chop Disabled (CHOP = 1) With CHOP = 1, chop is disabled and t

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 31 of 108 ADC Noise Performance with Chop Disabled (CHOP = 1) Table 14, Table 15, Table 16, and Tab

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 32 of 108 AUXILIARY ADC (ADUC845 ONLY ) Table 18. ADuC845 Typical Output RMS Noise (µV) vs. Update

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 33 of 108 of the input voltage on the analog input channel can be taken. When the resulting voltage

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 34 of 108 enabled for any SF word that yields an ADC throughput that is less than 20 Hz with chop e

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 35 of 108 Therefore, the full-scale endpoint calibration automatically subtracts the offset calibra

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 36 of 108 DATA OUTPUT CODING When the primary ADC is configured for unipolar operation, the output

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 37 of 108 TYPICAL PERFORMANCE CHARACTERISTICS –120–110–100–80–70–50–40–20–10–90–30–6000 10 20 30 4

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 38 of 108 –120–100–80–40–20–60010095908575708065605550404535302520101550FREQUENCY (Hz)AMPLITUDE (dB

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 39 of 108 FUNCTIONAL DESCRIPTION ADC SFR INTERFACE The ADCs are controlled and configured via a num

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 4 of 108 SPECIFICATIONS1 AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 40 of 108 ADCSTAT (ADC STATUS REGISTER) This SFR reflects the status of both ADCs including data re

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 41 of 108 ADCMODE (ADC MODE REGISTER) Used to control the operational mode of both ADCs. SFR Addre

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 42 of 108 Notes on the ADCMODE Register • Any change to the MD bits immediately resets both ADCs (

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 43 of 108 ADC0CON1 (PRIMARY ADC CONTROL REGISTER) ADC0CON1 is used to configure the primary ADC for

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 44 of 108 ADC0CON2 (PRIMARY ADC CHANNEL SELECT REGISTER) ADC0CON2 is used to select a reference so

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 45 of 108 ADC1CON (AUXILIARY ADC CONTROL REGISTER) (ADuC845 ONLY) ADC1CON is used to configure the

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 46 of 108 SF (ADC SINC FILTER CONTROL REGISTER) The SF register is used to configure the decimation

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 47 of 108 ICON (EXCITATION CURRENT SOURCES CONTROL REGISTER) The ICON register is used to configure

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 48 of 108 NONVOLATILE FLASH/EE MEMORY OVERVIEW The ADuC845/ADuC847/ADuC848 incorporate Flash/EE mem

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 49 of 108 40 60 70 90TJ JUNCTION TEMPERATURE (C)RETENTION(Years)25020015010050050 80 110300100ADI S

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 5 of 108 Parameter Min Typ Max Unit Conditions Normal Mode Rejection 50 Hz/60 Hz2 On

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 50 of 108 USER DOWNLOAD MODE (ULOAD) Figure 28 shows that it is possible to use the 62 kbytes of Fla

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 51 of 108 USING FLASH/EE DATA MEMORY The 4 kbytes of Flash/EE data memory are configured as 1024 pag

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 52 of 108 Example: Programming the Flash/EE Data Memory A user wants to program F3H into the second

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 53 of 108 DAC CIRCUIT INFORMATION The ADuC845/ADuC847/ADuC848 incorporate a 12-bit, voltage output

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 54 of 108 Using the DAC The on-chip DAC architecture consists of a resistor string DAC followed by a

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 55 of 108 SOURCE/SINK CURRENT (mA)30 5 10 15OUTPUT VOLTAGE (V)210DAC LOADED WITH 0000HDAC LOADED WIT

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 56 of 108 PWMCON PWM Control SFR SFR Address: AEH Power-On Default: 00H Bit Addressable: N

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 57 of 108 PWM Cycle Width High Byte (PWM1H) SFR Address: B4H Power-On Default: 00H Bit Addressa

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 58 of 108 Mode 3 (Twin 16-Bit PWM) In Mode 3, the PWM counter is fixed to count from 0 to 65536, gi

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 59 of 108 Mode 5 (Dual 8-Bit PWM) In Mode 5, the duty cycle and the resolution of the PWM outputs a

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 6 of 108 Parameter Min Typ Max Unit Conditions AUXILIARY ADC ANALOG INPUTS (ADuC845 Only)

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 60 of 108 ON-CHIP PLL (PLLCON) The ADuC845/ADuC847/ADuC848 are intended for use with a 32.768 kHz w

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 61 of 108 I2C SERIAL INTERFACE The ADuC845/ADuC847/ADuC848 support a fully licensed I2C serial inte

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 62 of 108 I2CADD—I2C Address Register 1 Function: Holds one of the I2C peripheral addresses for th

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 63 of 108 Hardware Slave Mode After reset, the ADuC845/ADuC847/ADuC848 default to hardware slave mo

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 64 of 108 SPI SERIAL INTERFACE The ADuC845/ADuC847/ADuC848 integrate a complete hardware serial per

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 65 of 108 SPICON—SPI Control Register SFR Address: F8H Power-On Default: 05H Bit Addressable:

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 66 of 108 USING THE SPI INTERFACE Depending on the configuration of the bits in the SPICON SFR sh

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 67 of 108 DUAL DATA POINTERS The parts incorporate two data pointers. The second data pointer is a

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 68 of 108 POWER SUPPLY MONITOR The power supply monitor, once enabled, monitors the DVDD and AVDD s

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 69 of 108 WATCHDOG TIMER The watchdog timer generates a device reset or interrupt within a reasonab

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 7 of 108 Parameter Min Typ Max Unit Conditions TRANSDUCER BURNOUT CURRENT SOURCES AIN

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 70 of 108 TIME INTERVAL COUNTER (TIC) A TIC is provided on-chip for counting longer intervals than

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 71 of 108 TIMECON—TIC Control Register SFR Address: A1H Power-On Default: 00H Bit Addressable:

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 72 of 108 I N T VA L —User Timer Interval Select Register Function: User code writes the required t

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 73 of 108 8052-COMPATIBLE ON-CHIP PERIPHERALS This section gives a brief overview of the various se

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 74 of 108 P2.5 and P2.6 can also be used as PWM outputs, while P2.7 can act as an alternate PWM clo

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 75 of 108 TIMERS/COUNTERS The ADuC845/ADuC847/ADuC848 have three 16-bit timer/ counters: Timer 0, T

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 76 of 108 TCON—Timer/Counter 0 and 1 Control Register SFR Address: 88H Power-On Default: 00H Bi

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 77 of 108 Timer/Counter 0 and 1 Operating Modes This section describes the operating modes for Time

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 78 of 108 T2CON—Timer/Counter 2 Control Register SFR Address: C8H Power-On Default: 00H Bit Add

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 79 of 108 Timer/Counter 2 Operating Modes The following sections describe the operating modes for T

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 8 of 108 Parameter Min Typ Max Unit Conditions LOGIC OUTPUTS (All Digital Outputs except XTAL

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 80 of 108 UART SERIAL INTERFACE The serial port is full duplex, meaning that it can transmit and re

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 81 of 108 Mode 0 (8-Bit Shift Register Mode) Mode 0 is selected by clearing both the SM0 and SM1 bit

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 82 of 108 Mode 3 (9-Bit UART with Variable Baud Rate) Mode 3 is selected by setting both SM0 and SM

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 83 of 108 Timer 3 Generated Baud Rates The high integer dividers in a UART block mean that high sp

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 84 of 108 T3FD—Timer 3 Fractional Divider Register See Table 57 for values. SFR Address: 9DH Po

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 85 of 108 INTERRUPT SYSTEM The ADuC845/ADuC847/ADuC848 provide nine interrupt sources with two prio

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 86 of 108 IEIP2—Secondary Interrupt Enable Register SFR Address: A9H Power-On Default: A0H Bit

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 87 of 108 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design cons

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 88 of 108 as op amps and voltage reference) can be powered from the AVDD supply line as well. DVDDA

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 89 of 108 • Cycling Power All registers are set to their default state and program exe-cution star

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 9 of 108 Parameter Min Typ Max Unit Conditions PWM −Fxtal 3 µA −Fvco 0.5

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 90 of 108 DGNDAGNDPLACE ANALOGCOMPONENTSHEREPLACE DIGITALCOMPONENTSHEREGNDPLACE ANALOGCOMPONENTSHERE

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 91 of 108 C1+V+C1–C2+C2–V–T2OUTR2INVCCGNDT1OUTR1INR1OUTT1INT2INR2OUTADM3202RS-232 INTERFACE11234567

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 92 of 108 The serial port debugger is fully contained on the device, unlike ROM monitor type debugg

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 93 of 108 DVDD0.1µFRESET ACTIVE HIGH.(NORMALLY OPEN)353443441kΩDVDD1kΩ2-PIN HEADER FOREMULATION ACC

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 94 of 108 QuickStart DEVELOPMENT SYSTEM The QuickStart Development System is an entry-level, low co

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 95 of 108 TIMING SPECIFICATIONS AC inputs during testing are driven at DVDD – 0.5 V for Logic 1 and

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 96 of 108 Table 65. EXTERNAL DATA MEMORY READ CYCLE Parameter 12.58 MHz Core Clock 6.29 MHz Core

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 97 of 108 Table 66. EXTERNAL DATA MEMORY WRITE CYCLE Parameter 12.58 MHz Core Clock 6.29 MHz Cor

ADuC845/ADuC847/ADuC848 Data Sheet Rev. C | Page 98 of 108 MSBtBUFSDATA (I/O)SCLK (I)STOPCONDITIONSTARTCONDITIONREPEATEDSTARTLSB ACK MSB1 2-7 8 9

Data Sheet ADuC845/ADuC847/ADuC848 Rev. C | Page 99 of 108 Table 68. SPI MASTER MODE TIMING (CPHA = 1) Parameter Min Typ Max Unit tSL